preliminary 8 mb (1024k x 8) mobl ? static ram cy62158dv mobl ? cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-05391 rev. *b revised january 24, 2004 features ? very high speed: 55 ns ? wide voltage range: 2.20v ? 3.60v ? ultra-low active power ? typical active current:1.5 ma @ f = 1 mhz ? typical active current: 12 ma @ f = f max (55-ns speed) ? ultra-low standby power ? easy memory expansion with ce 1 , ce 2 , and oe fea- tures ? automatic power-down when deselected ? cmos for optimum speed/power ? packages offered in a 48-ball bga, 48-pin tsopi, and 44-pin tsopii functional description [1] the cy62158dv is a high-per formance cmos static rams organized as 1024k words by 8 bits. this device features advanced circuit design to provide ultra-low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power-dow n feature that significantly reduces power consumption. the device can be put into standby mode reducing power consumption by more than 99% when deselected (ce 1 high or ce 2 low). writing to the device is accomplished by taking chip enable 1 (ce 1 ) and write enable (we ) inputs low and chip enable 2 (ce 2 ) high. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 19 ). reading from the device is accomplished by taking chip enable 1 (ce 1 ) and output enable (oe ) low and chip enable 2 (ce 2 ) high while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. the eight input/output pins (i/o 0 through i/o 7 ) are placed in a high-impedance state when the device is deselected (ce 1 low and ce 2 high), the outputs are disabled (oe high), or during a write operation (ce 1 low and ce 2 high and we low). see the truth table for a complete description of read and write modes. logic block diagram note: 1. for best practice recommendations, please refer to the cypress application note entitled system design guidelines , available at http://www.cypress.com. a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps data in drivers power down we oe i/o 0 i/o 1 i/o 2 i/o 3 1024k x 8 array i/o 7 i/o 6 i/o 5 i/o 4 a 0 a 14 a 13 a 16 a 18 a 15 a 17 a 9 a 19 ce 1 ce 2 a 10 a 11 a 12
preliminary cy62158dv mobl ? document #: 38-05391 rev. *b page 2 of 10 pin configuration [2,3] fbga 48tsopi 44 tsopii notes: 2. nc pins are not internally connected to the die. 3. dnu pins have to be left floating or tied to v ss to ensure proper application. top view a a we v cc a 11 a 10 a 6 a 0 a 3 ce 1 dnu dnu i/o 0 a 4 a 5 i/o 1 dnu i/o 2 i/o 3 dnu a 9 a 8 oe v ss a 7 dnu dnu ce 2 a 17 a 2 a 1 dnu v cc i/o 4 dnu i/o 5 i/o 6 dnu i/o 7 dnu a 15 a 14 a 13 a 12 nc a 18 a 19 3 2 6 5 4 1 d e b a c f g h a 16 dnu v ss we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 v cc a 19 a 18 a 17 a 16 a 4 a 3 oe v ss a 5 dnu a 2 ce 1 i/o 0 dnu dnu ce 2 a 1 a 0 18 17 20 19 i/o 1 27 28 25 26 22 21 23 24 v ss dnu i/o 2 i/o 3 dnu a 6 a 7 a8 v cc dnu i/o 7 i/o 6 i/o 5 i/o 4 dnu dnu a 10 a 11 a 12 a 13 a 15 a 14 a 9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a15 a14 a13 a12 a11 a10 a9 a8 nc dnu we ce 2 dnu bhe ble a18 a17 a7 a6 a5 a4 a3 a2 a1 a16 vss vss a19 i/o7 dnu i/o6 dnu i/o5 dnu i/o4 vcc dnu i/o3 dnu i/o2 dnu i/o1 dnu i/o0 oe vss ce 1 a0 top view top view
preliminary cy62158dv mobl ? document #: 38-05391 rev. *b page 3 of 10 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature .............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. ............ .......... 55c to +125c supply voltage to ground potential .?0.2v to v cc(max) + 0.2v dc voltage applied to outputs in high-z state [4] ............................ ?0.2v to v cc(max) + 0.2v dc input voltage [4] ......................... ?0.2v to v cc(max) + 0.2v output current into outputs (low)............................. 20 ma static discharge voltage......... .............. .............. ....... >2001v (per mil-std-883, method 3015) latch-up current...................................................... >200 ma operating range product range ambient temperature (t a ) v cc [5] cy62158dvl industrial ?40c to +85c 2.2v to 3.6v cy62158dvll product portfolio product v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( a) f = 1 mhz f = f max min. typ. [6] max. typ. [6] max. typ. [6] max. typ. [6] max. cy62158dvl 2.2 3.0 3.6 55 1.5 3 12 20 2 20 cy62158dvll 2.2 3.0 3.6 55 1.5 3 12 15 2 8 electrical characteristics over the operating range parameter description test conditions cy62158dv-55 unit min. typ. [6] max. v oh output high voltage i oh = ?0.1 ma v cc = 2.20v 2.0 v i oh = ?1.0 ma v cc = 2.70v 2.4 v v ol output low voltage i ol = 0.1 ma v cc = 2.20v 0.4 v i ol = 2.1ma v cc = 2.70v 0.4 v v ih [7] input high voltage v cc = 2.2v to 2.7v 1.8 v cc + 0.3v v v cc = 2.7v to 3.6v 2.2 v cc + 0.3v v v iil input low voltage v cc = 2.2v to 2.7v ?0.3 0.6 v v cc = 2.7v to 3.6v ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 a i oz output leakage current gnd < v o < v cc , output disabled ?1 +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = v ccmax i out = 0 ma cmos levels l1220ma ll 15 ma f = 1 mhz l 1.5 3 ma ll 3 ma i sb1 automatic ce power-down current ? cmos inputs ce 1 > v cc ? 0.2v, ce 2 < 0.2v v in > v cc ? 0.2v, v in < 0.2v) f = f max (address and data only), f = 0 (oe , and we ), v cc = 3.60v l220 a ll 2 8 i sb2 automatic ce power-down current ? cmos inputs ce 1 > v cc ? 0.2v or ce 2 < 0.2v, v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = 3.60v l220 a ll 2 8 notes: 4. v il(min.) = ?2.0v for pulse durations less than 20 ns. 5. full device ac operation requires linear vcc ramp from 0 to vcc(min) >= 500 s. 6. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25c. 7. v ih(max) = v cc +0.75v for pulse duration less than 20ns.
preliminary cy62158dv mobl ? document #: 38-05391 rev. *b page 4 of 10 capacitance [8] parameter description test conditions max. unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ.) 6 pf c out output capacitance 8 pf thermal resistance parameter description test conditions bga tsop ii tsop i unit ja thermal resistance [8] (junction to ambient) still air, soldered on a 3 x 4.5 inch, four-layer printed circuit board 55 tbd tbd c/w jc thermal resistance [8] (junction to case) 16 tbd tbd c/w ac test loads and waveforms parameters 2.50v 3.0v unit r1 16667 1103 ? r2 15385 1554 ? r th 8000 645 ? v th 1.20 1.75 v data retention characteristics (over the operating range) parameter description conditions min. typ. [6] max. unit v dr v cc for data retention 1.5 2.2v v i ccdr data retention current v cc = 1.5v ce 1 > v cc ? 0.2v or ce 2 < 0.2v v in > v cc ? 0.2v or v in < 0.2v l 10 a ll 4 a t cdr [8] chip deselect to data retention time 0 ns t r [9] operation recovery time t rc ns notes: 8. tested initially and after any design or proces s changes that may affect these parameters. 9. full device ac operation requires linear v cc ramp from v dr to v cc(min.) > 100 s or stable at v cc(min.) > 100 s. v cc v cc output r2 50 pf including jig and scope gnd 90% 10% 90% 10% output v th equivalent to: th venin equivalent all input pulses r th r1 fall time: 1 v/ns rise time: 1 v/ns
preliminary cy62158dv mobl ? document #: 38-05391 rev. *b page 5 of 10 data retention waveform switching characteristics over the operating range [10] parameter description 55 ns unit min. max. read cycle t rc read cycle time 55 ns t aa address to data valid 55 ns t oha data hold from address change 10 ns t ace ce 1 low and ce 2 high to data valid 55 ns t doe oe low to data valid 25 ns t lzoe oe low to low z [11] 5 ns t hzoe oe high to high z [11, 12] 20 ns t lzce ce 1 low and ce 2 high to low z [11] 10 ns t hzce ce 1 high or ce 2 low to high z [11, 12] 20 ns t pu ce 1 low and ce 2 high to power-up 0 ns t pd ce 1 high or ce 2 low to power-down 55 ns write cycle [13] t wc write cycle time 55 ns t sce ce 1 low and ce 2 high to write end 40 ns t aw address set-up to write end 40 ns t ha address hold from write end 0 ns t sa address set-up to write start 0 ns t pwe we pulse width 40 ns t sd data set-up to write end 25 ns t hd data hold from write end 0 ns t hzwe we low to high z [11, 12] 20 ns t lzwe we high to low z [11] 10 ns notes: 10. test conditions for all parameters other than tri-state paramete rs assume signal transition time of 3ns or less (1v/ns), tim ing reference levels of v cc(typ.) /2, input pulse levels of 0 to v cc(typ.) , and output loading of the specified i ol /i oh as shown in the ?ac test loads and waveforms? section. 11. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 12. t hzoe , t hzce , and t hzwe transitions are measured when the outputs enter a high impedance state.transition is measured +/-200mv from steady state volta ge. 13. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input se t-up and hold timing should be referenced to the edge of the signal that terminates the write. v cc(min) v cc(min) t cdr v dr > 1.5 v data retention mode t r ce 1 v cc ce 2 or
preliminary cy62158dv mobl ? document #: 38-05391 rev. *b page 6 of 10 switching waveforms notes: 14. device is continuously selected. oe , ce 1 = v il , ce 2 = v ih . 15. we is high for read cycle. 16. address valid prior to or coincident with ce 1 transition low and ce 2 transition high. address data out previous data valid data valid t rc t aa t oha read cycle no. 1 (address transition controlled) [14, 15] 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce 1 i cc i sb impedance address ce 2 data out supply current read cycle no. 2 (oe controlled) [15, 16] t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe valid data ce 1 address ce 2 we data i/o oe note [18] write cycle no. 1(we controlled) [13, 17, 19]
preliminary cy62158dv mobl ? document #: 38-05391 rev. *b page 7 of 10 truth table ce 1 ce 2 we oe inputs/outputs mode power h x x x high z deselect/power-down standby (i sb ) x l x x high z deselect/power-down standby (i sb ) l h h l data out (i/o 0 -i/o 7 ) read active (i cc ) l h h h high z output disabled active (icc) l h l x data in (i/o 0 -i/o 7 ) write active (icc) notes: 17. data i/o is high impedance if oe = v ih . 18. during this period, the i/os are in output state and input signals should not be applied. 19. if ce 1 goes high or ce 2 goes low simultaneously with we high, the output remains in high-impedance state. switching waveforms (continued) t wc valid data t aw t sa t pwe t ha t hd t sd t sce ce 1 address ce 2 we data i/o write cycle no. 2(ce 1 or ce 2 controlled) [13, 17, 19] oe valid data t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce 1 address ce 2 we data i/o note [18] write cycle no. 3 (we controlled, oe low) [19]
preliminary cy62158dv mobl ? document #: 38-05391 rev. *b page 8 of 10 ordering information speed (ns) ordering code package name package type operating range 55 cy62158dvl-55bvi bv48a 48-ball fine pitch bga (6 mm 8mm 1 mm) industrial cy62158dvll-55bvi 55 cy62158dvl-55zi z-48 48 pin tsop i industrial cy62158dvll-55zi 55 cy62158dvl-55zsi zs-44 44 pin tsop ii industrial cy62158dvll-55zsi package diagrams 48-lead vfbga (6 x 8 x 1 mm) bv48a 51-85150-*b
preliminary cy62158dv mobl ? document #: 38-05391 rev. *b page 9 of 10 ? cypress semiconductor corporation, 2003. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. mobl is a registered trademark, and more battery life is a trademark, of cypress semicond uctor. all product and company names mentioned in this document are tr ademarks of their respective holders. package diagrams (continued) 51-85183-*a 48-pin tsop i z48 44-pin tsop ii zs44 51-85087-*a
preliminary cy62158dv mobl ? document #: 38-05391 rev. *b page 10 of 10 document history page document title:cy62158dv mobl ? 8 mb (1024k x 8) mobl ? static ram document number: 38-05391 rev. ecn no. issue date orig. of change description of change ** 126293 05/22/03 hrt new data sheet *a 131014 11/25/03 cbd change from advance to preliminary *b 133114 01/24/04 cbd minor c hange: mpn change and upload
|
